exist to any major extent in PMOS LDOs (since PMOS transistors are controlled by voltage level, not current).

In the example shown, the regulator delivers 5V × 1A, or 5W to the load. With a dropout voltage of 1V, the input power is 6V times the same 1A, or 6W. In terms of power efficiency, this can be calculated as:

where POUT and PIN are the total output and input powers, respectively.

In these sample calculations, the relatively small portion of power related to Iground will be ignored for simplicity, since this power is relatively small. In an actual design, this simplifying step may not be justified.

In the case shown, the efficiency would be 100 × 5/6, or about 83%. But by contrast, if an LDO were to be used with a dropout voltage of 0.1V instead of 1V, the input voltage can then be allowed to go as low as 5.1V. The new efficiency for this condition then becomes 100 × 5/5.1, or 98%. It is obvious that an LDO can potentially greatly enhance the power efficiency of linear voltage regulator systems.

A traditional LDO architecture is shown in below Figure, and is generally representative of actual parts employing either a PNP pass device as shown, or alternately, a PMOS device.



In DC terms, perhaps the major issue is the type of pass device used, which influences dropout voltage and ground current. If a lateral PNP device is used for
Q1, the will be low, sometimes only on the order or 10 or so. Since Q1 is driven from the collector of Q2, the relatively high base current demanded by a lateral PNP results in relatively high emitter current in Q2, or a high Iground. For a typical lateral PNP based regulator operating with a 5V/150mA output, Iground will be typically ~18mA, and can be as high as 40mA. To compound the problem of high
Iground in PNP LDOs, there is also the "spike" in Iground, as the regulator is operating within its dropout region. Under such conditions, the output voltage is out of tolerance, and the regulation loop forces higher drive to the pass device, in an attempt to maintain loop regulation. This results in a substantial spike upward in
Iground, which is typically internally limited by the regulator’s saturation control circuits.

PMOS pass devices do not demonstrate a similar current spike in Iground, since they are voltage controlled. But, while devoid of the Iground spike, PMOS pass devices do have some problems of their own. Problem number one is that high
quality, low RON, low threshold PMOS devices generally aren’t compatible with
many IC processes. This makes the best technical choice for a PMOS pass device an
external part, driven from the collector of Q2 in the figure. This introduces the term
"LDO controller", where the LDO architecture is completed by an external pass
device. While in theory NMOS pass devices would offer lower RON choice options,
they also demand a boosted voltage supply to turn on, making them impractical for
a simple LDO. PMOS pass devices are widely available in low both RON and low
threshold forms, with current levels up to several amperes. They offer the potential
of the lowest dropout of any device, since dropout can always be lowered by picking a
lower RON part.

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