The dropout voltage of lateral PNP pass devices is reasonably good, typically around
300mV at 150mA, with a maximum of 600mV. These levels are however
considerably bettered in regulators using vertical PNPs, which have a typical of
~150 at currents of 200mA. This leads directly to an Iground of 1.5mA at the 200mA
output current. The dropout voltage of vertical PNPs is also an improvement vis-àvis
that of the lateral PNP regulator, and is typically 180mV at 200mA, with a
maximum of 400mV.

There are also major AC performance issues to be dealt with in the LDO
architecture shown above.

This topology has an inherently high output impedance, due to the operation of the PNP pass device in a common-emitter (or common-source with a PMOS device) mode. In either case, this factor causes the regulator to appear as a high source impedance to the load.

The internal compensation capacitor of the regulator, CCOMP, forms a fixed
frequency pole, in conjunction with the gm of the error amplifier. In addition, load
capacitance CL forms an output pole, in conjunction with RL. This particular pole,
because it is a second (and sometimes variable) pole of a two-pole system, is the
source of a major LDO application problem. The CL pole can strongly influence the
overall frequency response of the regulator, in ways that are both useful as well as
detrimental. Depending upon the relative positioning of the two poles in the
frequency domain, along with the relative value of the ESR of capacitor CL, it is
quite possible that the stability of the system can be compromised for certain
combinations of CL and ESR. Note that CL is shown here as a real capacitor, which
is actually composed of a pure capacitance plus the series parasitic resistance ESR.
Without a heavy duty exercise into closed-loop stability analysis, it can safely be
said that LDOs, like other feedback systems, need to satisfy certain basic stability
criteria. One of these is the gain-versus-frequency rate-of-change characteristic in
the region approaching the system’s unity loop gain crossover point. For the system
to be closed loop stable, the phase shift must be less than 180at the point of unity
gain. In practice, a good feedback design needs to have some phase margin,
generally 45or more to allow for various parasitic effects. While a single pole
system is intrinsically stable, two pole systems are not necessarily so—they may in
fact be stable, or they may also be unstable. Whether or not they are stable for a
given instance is highly dependent upon the specifics of their gain-phase
characteristics. If the two poles of such a system are widely separated in terms of frequency, stability may not be a serious problem.

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